1. Field of the Invention
The present invention relates to a split transaction protocol for the Peripheral Component Interconnect bus using only one sideband signal.
2. Description of the Related Art
In many computer systems to date, a processor bus connects the processor to memory and usually to a second level (L2) cache to comprise a central processing unit (CPU) subsystem. The processor bus interfaces with input-output (I/O) device, such as a disk controller, CD-ROM, video and graphics cards, local area networks (LANs), to name a few, through an expansion bus, such as an Extended Industry Standard Architecture (EISA), Industry Standard Architecture (ISA), or MicroChannel bus. In spite of the high processor speeds, system performance is often limited by the speed of the much slower I/O devices because of the speed at which the processor can transmit or receive data to and from those devices.
To improve data flow and to better utilize the high clock rates of the newer processors, developers have turned to the local bus. A local bus resides logically between the processor bus and the expansion bus, connecting the buses through bridge circuitry. A number of standards have been developed, including VESA's (Video Equipment Standard Association) VL-Bus, Intel Corporation's PCI (Peripheral Component Interconnect), and Apple Computer Company's QuickRing. For example, with a PCI bus, the CPU subsystem interfaces with the PCI bus through a PCI bridge. Also often directly connected to PCI bus are audio, video, graphics, SCSI, and LAN subsystems. Further, an expansion bus chip set forms the bridge circuitry connecting the PCI bus to the standard expansion bus.
The PCI bus is a physical interconnect mechanism intended for use between highly integrated peripheral controller components and processor/memory systems. The intent was originally to standardize a local bus on which a large variety of input/output (I/O) components can directly connect together without glue logic. Further, the PCI bus was intended as a standard interface at the component level in much the same way that ISA, EISA or Micro Channel is a standard interface at the board level. PCI was not intended to replace standard expansion buses, which have, so far, remained the primary means of adding expansion boards when necessary. Nonetheless, the currently implemented version includes PCI connectors for receiving PCI compatible boards. Many of the I/O functions traditionally coupled through the expansion bus have migrated or will soon migrate to the PCI bus.
In discussing PCI, a few conventions will be observed. A signal name in all capital letters indicates a defined bus signal. For example, CLK and AD[31..00], respectively, represent the PCI clock signal and the 32 PCI address-data signals. These signals are physically asserted active high. The PCI specification defines some signals as active low following the special signal type definitions of PCI. These signals' physical lines are indicated in their negated state by being followed by a pound (#) sign. For example, when two PCI defined signals FRAME# and DEVSEL# go low, the signals are considered asserted initiating a frame and a device select, respectively. These conventions are consistent with the description of PCI found in the Peripheral Component Interconnect (PCI) Revision 2.0 Specification, Production Version, Revision 2.0, Apr. 30, 1993, .COPYRGT.1993 PCI Special Interest Group, which is hereby incorporated by reference.
According to the PCI specification, PCI provides an exclusive access mechanism, which allows non-exclusive accesses to proceed in the face of exclusive accesses. This is referred to as a resource lock. This allows subsequent PCI bus masters to hold a resource lock on a slave or target device across several instructions or accesses without interfering with non-exclusive, real time data transfers, such as video. A hardware lock is indicated by a signal referred to as LOCK#, which indicates an atomic operation that may require multiple transactions to occur. Therefore, in a resource lock, exclusivity of an access is guaranteed by the target device and not by excluding all other masters or agents from accessing the PCI bus.
According to the current PCI specification, if a PCI master performs a read to a target device which requires a substantial amount of time to complete the read cycle, the PCI bus is dedicated to that access until the data is returned. In the interim, the PCI bus is essentially idle. The target device could assert a disconnect or retry to indicate to the master that it is unable to perform the read within the latency requirements of the PCI bus. However, if no other devices require the bus, thrashing of the master-target might occur where the master keeps interrupting the target on several subsequent transactions until the data is finally available. Also, the master is unable to distinguish the normal disconnect or retry where the target is unable to perform the operation, from the long latency case where the operation simply takes more time. Locking the device is not desirable for just any case, since the device may be performing other transactions, such as an EISA bus master, and thus may simply be unable to handle the request at that time. Locking the target in that case may cause a fatal error.
When a target device is locked, and another master attempts to access that target, the currently locked target will respond by asserting a retry or disconnect transaction to prevent the access. Furthermore, the LOCK# signal is normally supposed to be released if a retry is signaled before a data phase has completed. Therefore, there are no mechanisms for allowing the master to release the bus for other non-exclusive accesses during a read to a long latency device, so that all other devices must wait while the bus is essentially idle.
It is desired to provide a mechanism to allow non-exclusive accesses to proceed during a read to a long latency device.